Recently, semiconductor memory devices are being extensively used. For example, one representative semiconductor memory device is an EEPROM (electrically erasable programmable read-only memory) capable of writing, reading and erasing data by applying differentiated control voltage.
FIG. 1 is a circuit diagram schematically illustrating elements of a semiconductor device control circuit, and FIG. 2 is a data table illustrating voltage for each applied mode for controlling the semiconductor device.
Referring to FIG. 1, a semiconductor memory device, i.e. an EEPROM 10, has three voltage control terminals CG. RBL and TG for data writing, reading and erasing operations. The voltage control terminal TG connects to a first transistor 20, the voltage control terminal RBL connects to a second transistor 30, and the voltage control terminal CG connects to a third transistor 40.
The transistors 20, 30 and 40 are typically NMOS (n-channel metal oxide semiconductors) transistors, and selectively transfer an external signal to the semiconductor memory device 10 in order to perform writing, reading and erasing operations.
Control terminals (e.g. gates) of the transistors 20, 30 and 40 are connected with a first external terminal 50 to receive an operating voltage. The first transistor 20 connected with the voltage control terminal TG of the EEPROM 10 is also connected to a second external terminal 60.
Further, the second transistor 30 connected with the voltage control terminal RBL of the EEPROM 10 is also connected to a third external terminal 70, and the third transistor 40 connected with the voltage control terminal CG is also connected to a fourth external terminal 80.
As shown in FIG. 2, in order to write data in the EEPROM 10, a voltage of about 12V is applied to the fourth external terminal 80. The applied voltage is input to the voltage control terminal CG through a switching operation of the third transistor 40.
Further, in order to erase data from the EEPROM 10, a voltage of about 12V is applied to the second external terminal 60. The applied voltage is input to the voltage control terminal TG through a switching operation of the first transistor 20.
Further, in order to read data from the EEPROM 10, voltage of about 2V is applied to the third external terminal 70 and voltage of about 3.3V is applied to the fourth external terminal 80. The applied voltages 2V and 3.3V are input to the voltage control terminals RBL and CG through the second and third transistors 30 and 40, respectively.
However, the first and third transistors 20 and 40 cannot switch the voltage of 12V to the voltage control terminals TG and CG before receiving operating voltage of 12V or more through the first external terminal 50.
At this time, a threshold voltage VT exists in the first and third transistors 20 and 40. Thus, the operating voltage applied through the first external terminal 50 must be greater than “12V+VT”.
For this reason, the semiconductor device control circuit requires an additional voltage generator for supplying voltage of “12V+VT” or more. This is often accomplished through a regulator or a voltage switch circuit using a clock signal.
FIG. 3 is a circuit diagram schematically illustrating elements of a voltage switch circuit according to a related art that may be connected with the semiconductor device control circuit of FIG. 1, and FIG. 4 is a graph illustrating signals of the voltage switch circuit of FIG. 3.
Referring to FIG. 3, the voltage switch circuit includes seven transistors a first transistor 125, a second transistor 130, a third transistor 135, a fourth transistor 140, a fifth transistor 145, a sixth transistor 146 and a seventh transistor 147. In addition, the voltage switch circuit includes four external terminals: a first external terminal 105, a second external terminal 120, a third external terminal 110, and a fourth external terminal 115.
The first external terminal 105 of the voltage switch circuit may be connected to the first external terminal 50 of the semiconductor device control circuit of FIG. 1. The fourth to seventh transistors 140, 145, 146 and 147 connect to the first external terminal 105 of the voltage switch circuit through a Zener diode 155.
The Zener diode 155 and the fourth to seventh transistors 140, 145, 146 and 147 constitute a circuit for generating the voltage of “12V+VT” or more by boosting the input voltage.
The second external terminal 120 of the voltage switch circuit receives an enable signal. The second external terminal 120 connects to the source of first transistor 125. The drain of the first transistor 125 is connected between the first external terminal 105 and the Zener diode 155 at a node N1.
The node N1 is connected to the drain of the second transistor 130. The gate of the second transistor 130 is connected to the third external terminal 110 through a capacitor 150. The third external terminal 110 receives a clock signal.
The source of the second transistor 130 is connected to the source of the third transistor 135. The drain of the third transistor 135 is connected to the fourth external terminal 115 to which an operating voltage VPP is applied.
In addition, the gate of the second transistor 130 connects to the sources of both the third transistor 135 and the second transistor 130 at a node N2. Further, the gate of the third transistor 135 is connected to the node N1.
Hereinafter, an operation of the voltage switch circuit having the construction as described above will be briefly described.
First, if VSS (often a ground or 0V signal) is input through the second external terminal 120 as an enable signal, the first transistor 125, which receives the VSS through a conduction terminal (its source) and receives VDD through a control terminal (gate) thereof, is turned on. Thus, the VSS is transferred to the first external terminal 105 through the drain of the first transistor 125.
In such a case, the semiconductor device control circuit does not receive a voltage of “12V+VT” or more.
Second, if the VDD voltage is input through the second external terminal 120, the first transistor 125 is turned off, and one terminal of the capacitor 150 continuously receives the VDD and the VSS voltage values according to a boosting clock signal input through the third external terminal 110.
Thus, voltage of the node N2 is boosted.
The voltage boosted in the node N2 is applied to the control terminal (gate) of the second transistor 130. Then, as the second transistor 130 operates (is on), high voltage current flows in the first external terminal 105.
The high voltage current is identical to the sum of breakdown voltage of the Zener diode 155 and threshold voltages of the fourth to seventh transistors 140, 145, 146 and 147. Thus, the voltage of “12V+VT” or more can be supplied to the semiconductor device control circuit.
Referring to FIG. 4, the clock signal shown in graph “A” is input to the third external terminal 110. The graph “A” appears as a solid block between VSS and VDD voltage values because of the frequency of the clock signal. The VDD and VSS enable signal shown in graph “B” are periodically input through the second external terminal 120.
Referring to graph “C”, if the VSS is input, low voltage is generated and transferred to the first external terminal 105. This corresponds to the first operation as described above.
In graph “C”, when the VDD is input, the high voltage, i.e. the voltage of “12V+VT” or more, is generated and transferred to the first external terminal 105. This corresponds to the second operation as described above.
Since the voltage switch circuit as described above requires a plurality of devices, the size and area of the circuit is increased and a limitation exists in the minimization of the chip size.
Further, since the current of high voltage generated in the voltage switch circuit is affected by the breakdown voltage of the Zener diode 155 and the threshold voltages of the transistors 140, 145, 146 and 147, controlling a voltage numerical value may be difficult. Furthermore, since the high voltage current is sensitive to peripheral conditions such as temperature, the voltage may not be stably generated.